1. Digital Signals and Gates

While the binary numeration system is an interesting mathematical abstraction, we haven’t yet seen its practical application to electronics. This chapter is devoted to just that: practically applying the concept of binary bits to circuits. What makes binary numeration so important to the application of digital electronics is the ease in which bits may be represented in physical terms. Because a binary bit can only have one of two different values, either 0 or 1, any physical medium capable of switching between two saturated states may be used to represent a bit. Consequently, any physical system capable of representing binary bits is able to represent numerical quantities, and potentially has the ability to manipulate those numbers. This is the basic concept underlying digital computing.

Electronic circuits are physical systems that lend themselves well to the representation of binary numbers. Transistors, when operated at their bias limits, may be in one of two different states: either cutoff (no controlled current) or saturation (maximum controlled current). If a transistor circuit is designed to maximize the probability of falling into either one of these states (and not operating in the linear, or active, mode), it can serve as a physical representation of a binary bit. A voltage signal measured at the output of such a circuit may also serve as a representation of a single bit, a low voltage representing a binary "0" and a (relatively) high voltage representing a binary "1." Note the following transistor circuit:

Figure 1. Transistor in saturation.

In this circuit, the transistor is in a state of saturation by virtue of the applied input voltage (5 volts) through the two-position switch. Because its saturated, the transistor drops very little voltage between collector and emitter, resulting in an output voltage of (practically) 0 volts. If we were using this circuit to represent binary bits, we would say that the input signal is a binary "1" and that the output signal is a binary "0." Any voltage close to full supply voltage (measured in reference to ground, of course) is considered a "1" and a lack of voltage is considered a "0." Alternative terms for these voltage levels are high (same as a binary "1") and low (same as a binary "0"). A general term for the representation of a binary bit by a circuit voltage is logic level.

Moving the switch to the other position, we apply a binary "0" to the input and receive a binary "1" at the output:

Figure 2. Transistor in cutoff.

What we’ve created here with a single transistor is a circuit generally known as a logic gate, or simply gate. A gate is a special type of amplifier circuit designed to accept and generate voltage signals corresponding to binary 1’s and 0’s. As such, gates are not intended to be used for amplifying analog signals (voltage signals between 0 and full voltage). Used together, multiple gates may be applied to the task of binary number storage (memory circuits) or manipulation (computing circuits), each gate’s output representing one bit of a multi-bit binary number. Just how this is done is a subject for a later chapter. Right now it is important to focus on the operation of individual gates.

The gate shown here with the single transistor is known as an inverter, or NOT gate, because it outputs the exact opposite digital signal as what is input. For convenience, gate circuits are generally represented by their own symbols rather than by their constituent transistors and resistors. The following is the symbol for an inverter: ]

Figure 3. Inverter/NOT gate.

An alternative symbol for an inverter is shown here:

Figure 4. Alternative symbol for the inverter/NOT gate.

Notice the triangular shape of the gate symbol, much like that of an operational amplifier. As was stated before, gate circuits actually are amplifiers. The small circle, or "bubble" shown on either the input or output terminal is standard for representing the inversion function. As you might suspect, if we were to remove the bubble from the gate symbol, leaving only a triangle, the resulting symbol would no longer indicate inversion, but merely direct amplification. Such a symbol and such a gate actually do exist, and it is called a buffer, the subject of the next section.

Like an operational amplifier symbol, input and output connections are shown as single wires, the implied reference point for each voltage signal being "ground." In digital gate circuits, ground is almost always the negative connection of a single voltage source (power supply). Dual, or "split," power supplies are seldom used in gate circuitry. Because gate circuits are amplifiers, they require a source of power to operate. Like operational amplifiers, the power supply connections for digital gates are often omitted from the symbol for simplicity’s sake. If we were to show all the necessary connections needed for operating this gate, the schematic would look something like this:

Figure 5. All necessary connections shown.

Power supply conductors are rarely shown in gate circuit schematics, even if the power supply connections at each gate are. Minimizing lines in our schematic, we get this:

Figure 6. All necessary connections not shown.

"Vcc" stands for the constant voltage supplied to the collector of a bipolar junction transistor circuit, in reference to ground. Those points in a gate circuit marked by the label "Vcc" are all connected to the same point, and that point is the positive terminal of a DC voltage source, usually 5 volts.

As we will see in other sections of this chapter, there are quite a few different types of logic gates, most of which have multiple input terminals for accepting more than one signal. The output of any gate is dependent on the state of its input(s) and its logical function.

One common way to express the particular function of a gate circuit is called a truth table. Truth tables show all combinations of input conditions in terms of logic level states (either "high" or "low," "1" or "0," for each input terminal of the gate), along with the corresponding output logic level, either "high" or "low." For the inverter, or NOT, circuit just illustrated, the truth table is very simple indeed:

Figure 7. NOT gate truth table.

Truth tables for more complex gates are, of course, larger than the one shown for the NOT gate. A gate’s truth table must have as many rows as there are possibilities for unique input combinations. For a single-input gate like the NOT gate, there are only two possibilities, 0 and 1. For a two input gate, there are four possibilities (00, 01, 10, and 11), and thus four rows to the corresponding truth table. For a three-input gate, there are eight possibilities (000, 001, 010, 011, 100, 101, 110, and 111), and thus a truth table with eight rows are needed. The mathematically inclined will realize that the number of truth table rows needed for a gate is equal to 2 raised to the power of the number of input terminals.


  • In digital circuits, binary bit values of 0 and 1 are represented by voltage signals measured in reference to a common circuit point called ground. An absence of voltage represents a binary "0" and the presence of full DC supply voltage represents a binary "1."

  • A logic gate, or simply gate, is a special form of amplifier circuit designed to input and output logic level voltages (voltages intended to represent binary bits). Gate circuits are most commonly represented in a schematic by their own unique symbols rather than by their constituent transistors and resistors.

  • Just as with operational amplifiers, the power supply connections to gates are often omitted in schematic diagrams for the sake of simplicity.

  • A truth table is a standard way of representing the input/output relationships of a gate circuit, listing all the possible input logic level combinations with their respective output logic levels.

2. The NOT Gate

The single-transistor inverter circuit illustrated earlier is actually too crude to be of practical use as a gate. Real inverter circuits contain more than one transistor to maximize voltage gain (so as to ensure that the final output transistor is either in full cutoff or full saturation), and other components designed to reduce the chance of accidental damage.

Shown here is a schematic diagram for a real inverter circuit, complete with all necessary components for efficient and reliable operation:

Figure 8. Practical inverter/NOT circuit (A).

This circuit is composed exclusively of resistors, diodes and bipolar transistors. Bear in mind that other circuit designs are capable of performing the NOT gate function, including designs substituting field-effect transistors for bipolar (discussed later in this chapter).

Let’s analyze this circuit for the condition where the input is "high," or in a binary "1" state. We can simulate this by showing the input terminal connected to Vcc through a switch:

Figure 9. Practical inverter/NOT circuit (B).

In this case, diode D1 will be reverse-biased, and therefore not conduct any current. In fact, the only purpose for having D1 in the circuit is to prevent transistor damage in the case of a negative voltage being impressed on the input (a voltage that is negative, rather than positive, with respect to ground). With no voltage between the base and emitter of transistor Q1, we would expect no current through it, either. However, as strange as it may seem, transistor Q1 is not being used as is customary for a transistor. In reality, Q1 is being used in this circuit as nothing more than a back-to-back pair of diodes. The following schematic shows the real function of Q1:

Figure 10. Practical inverter/NOT circuit (C).

The purpose of these diodes is to "steer" current to or away from the base of transistor Q2, depending on the logic level of the input. Exactly how these two diodes are able to "steer" current isn’t exactly obvious at first inspection, so a short example may be necessary for understanding. Suppose we had the following diode/resistor circuit, representing the base-emitter junctions of transistors Q2 and Q4 as single diodes, stripping away all other portions of the circuit so that we can concentrate on the current "steered" through the two back-to-back diodes:

Figure 11. Practical inverter/NOT circuit (D).

With the input switch in the "up" position (connected to Vcc), it should be obvious that there will be no current through the left steering diode of Q1, because there isn’t any voltage in the switch-diode-R1-switch loop to motivate electrons to flow. However, there will be current through the right steering diode of Q1, as well as through Q2's base-emitter diode junction and Q4's base-emitter diode junction:

Figure 12. Practical inverter/NOT circuit (E).

This tells us that in the real gate circuit, transistors Q2 and Q4 will have base current, which will turn them on to conduct collector current. The total voltage dropped between the base of Q1 (the node joining the two back-to-back steering diodes) and ground will be about 2.1 volts, equal to the combined voltage drops of three PN junctions: the right steering diode, Q2's base-emitter diode, and Q4's base-emitter diode.

Now, let’s move the input switch to the "down" position and see what happens:

Figure 13. Practical inverter/NOT circuit (F).

If we were to measure current in this circuit, we would find that all of the current goes through the left steering diode of Q1 and none of it through the right diode. Why is this? It still appears as though there is a complete path for current through Q4's diode, Q2's diode, the right diode of the pair, and R1, so why will there be no current through that path?

Remember that PN junction diodes are very nonlinear devices: they do not even begin to conduct current until the forward voltage applied across them reaches a certain minimum quantity, approximately 0.7 volts for silicon and 0.3 volts for germanium. And then when they begin to conduct current, they will not drop substantially more than 0.7 volts. When the switch in this circuit is in the "down" position, the left diode of the steering diode pair is fully conducting, and so it drops about 0.7 volts across it and no more.

Figure 14. Practical inverter/NOT circuit (G).

Recall that with the switch in the "up" position (transistors Q2 and Q4 conducting), there was about 2.1 volts dropped between those same two points (Q1's base and ground), which also happens to be the minimum voltage necessary to forward-bias three series-connected silicon PN junctions into a state of conduction. The 0.7 volts provided by the left diode’s forward voltage drop is simply insufficient to allow any electron flow through the series string of the right diode, Q2's diode, and the R3//Q4 diode parallel subcircuit, and so no electrons flow through that path. With no current through the bases of either transistor Q2 or Q4, neither one will be able to conduct collector current: transistors Q2 and Q4 will both be in a state of cutoff.

Consequently, this circuit configuration allows 100 percent switching of Q2 base current (and therefore control over the rest of the gate circuit, including voltage at the output) by diversion of current through the left steering diode.

In the case of our example gate circuit, the input is held "high" by the switch (connected to Vcc), making the left steering diode (zero voltage dropped across it). However, the right steering diode is conducting current through the base of Q2, through resistor R1:

Figure 15. Practical inverter/NOT circuit (H).

With base current provided, transistor Q2 will be turned "on." More specifically, it will be saturated by virtue of the more-than-adequate current allowed by R1 through the base. With Q2 saturated, resistor R3 will be dropping enough voltage to forward-bias the base-emitter junction of transistor Q4, thus saturating it as well:

Figure 16. Practical inverter/NOT circuit (I).

With Q4 saturated, the output terminal will be almost directly shorted to ground, leaving the output terminal at a voltage (in reference to ground) of almost 0 volts, or a binary "0" ("low") logic level. Due to the presence of diode D2, there will not be enough voltage between the base of Q3 and its emitter to turn it on, so it remains in cutoff.

Let’s see now what happens if we reverse the input’s logic level to a binary "0" by actuating the input switch:

Figure 17. Practical inverter/NOT circuit (J).

Now there will be current through the left steering diode of Q1 and no current through the right steering diode. This eliminates current through the base of Q2, thus turning it off. With Q2 off, there is no longer a path for Q4 base current, so Q4 goes into cutoff as well. Q3, on the other hand, now has sufficient voltage dropped between its base and ground to forward-bias its base-emitter junction and saturate it, thus raising the output terminal voltage to a "high" state. In actuality, the output voltage will be somewhere around 4 volts depending on the degree of saturation and any load current, but still high enough to be considered a "high" (1) logic level.

With this, our simulation of the inverter circuit is complete: a "1" in gives a "0" out, and vice versa.

The astute observer will note that this inverter circuit’s input will assume a "high" state of left floating (not connected to either Vcc or ground). With the input terminal left unconnected, there will be no current through the left steering diode of Q1, leaving all of R1's current to go through Q2's base, thus saturating Q2 and driving the circuit output to a "low" state:

Figure 18. Practical inverter/NOT circuit (K).

The tendency for such a circuit to assume a high input state if left floating is one shared by all gate circuits based on this type of design, known as Transistor-to-Transistor Logic, or TTL. This characteristic may be taken advantage of in simplifying the design of a gate’s output circuitry, knowing that the outputs of gates typically drive the inputs of other gates. If the input of a TTL gate circuit assumes a high state when floating, then the output of any gate driving a TTL input need only provide a path to ground for a low state and be floating for a high state. This concept may require further elaboration for full understanding, so I will explore it in detail here.

A gate circuit as we have just analyzed has the ability to handle output current in two directions: in and out. Technically, this is known as sourcing and sinking current, respectively. When the gate output is high, there is continuity from the output terminal to Vcc through the top output transistor (Q3), allowing electrons to flow from ground, through a load, into the gate’s output terminal, through the emitter of Q3, and eventually up to the Vcc power terminal (positive side of the DC power supply):

Figure 19. Inverter gate sourcing current (A).

To simplify this concept, we may show the output of a gate circuit as being a double-throw switch, capable of connecting the output terminal either to Vcc or ground, depending on its state. For a gate outputting a "high" logic level, the combination of Q3 saturated and Q4 cutoff is analogous to a double-throw switch in the "Vcc" position, providing a path for current through a grounded load:

Figure 20. Inverter gate sourcing current (B).

Please note that this two-position switch shown inside the gate symbol is representative of transistors Q3 and Q4 alternately connecting the output terminal to Vcc or ground, not of the switch previously shown sending an input signal to the gate!

Conversely, when a gate circuit is outputting a "low" logic level to a load, it is analogous to the double-throw switch being set in the "ground" position. Current will then be going the other way if the load resistance connects to Vcc: from ground, through the emitter of Q4, out the output terminal, through the load resistance, and back to Vcc. In this condition, the gate is said to be sinking current:

Figure 21. Inverter gate sinking current (A).
Figure 22. Inverter gate sinking current (B).

The combination of Q3 and Q4 working as a "push-pull" transistor pair (otherwise known as a totem pole output) has the ability to either source current (draw in current to Vcc) or sink current (output current from ground) to a load. However, a standard TTL gate input never needs current to be sourced, only sunk. That is, since a TTL gate input naturally assumes a high state if left floating, any gate output driving a TTL input need only sink current to provide a "0" or "low" input, and need not source current to provide a "1" or a "high" logic level at the input of the receiving gate:

Figure 23. TTL gate input never needs current to be sourced, only sunk (A).
Figure 24. TTL gate input never needs current to be sourced, only sunk (B).
Figure 25. TTL gate input never needs current to be sourced, only sunk (C).

This means we have the option of simplifying the output stage of a gate circuit so as to eliminate Q3 altogether. The result is known as an open-collector output:

Figure 26. Inverter circuit with open-collector output (A).

To designate open-collector output circuitry within a standard gate symbol, a special marker is used. Shown here is the symbol for an inverter gate with open-collector output:

Figure 27. Inverter circuit with open-collector output (B).

Please keep in mind that the "high" default condition of a floating gate input is only true for TTL circuitry, and not necessarily for other types, especially for logic gates constructed of field-effect transistors.


  • An inverter, or NOT, gate is one that outputs the opposite state as what is input. That is, a "low" input (0) gives a "high" output (1), and vice versa.

  • Gate circuits constructed of resistors, diodes and bipolar transistors as illustrated in this section are called TTL. TTL is an acronym standing for Transistor-to-Transistor Logic. There are other design methodologies used in gate circuits, some which use field-effect transistors rather than bipolar transistors.

  • A gate is said to be sourcing current when it provides a path for current between the output terminal and the positive side of the DC power supply (Vcc). In other words, it is connecting the output terminal to the power source (+V).

  • A gate is said to be sinking current when it provides a path for current between the output terminal and ground. In other words, it is grounding (sinking) the output terminal.

  • Gate circuits with totem pole output stages are able to both source and sink current. Gate circuits with open-collector output stages are only able to sink current, and not source current. Open-collector gates are practical when used to drive TTL gate inputs because TTL inputs don’t require current sourcing.

3. The "Buffer" Gate

If we were to connect two inverter gates together so that the output of one fed into the input of another, the two inversion functions would "cancel" each other out so that there would be no inversion from input to final output:

Figure 28. Double inversion.

While this may seem like a pointless thing to do, it does have practical application. Remember that gate circuits are signal amplifiers, regardless of what logic function they may perform. A weak signal source (one that is not capable of sourcing or sinking very much current to a load) may be boosted by means of two inverters like the pair shown in the previous illustration. The logic level is unchanged, but the full current-sourcing or -sinking capabilities of the final inverter are available to drive a load resistance if needed.

For this purpose, a special logic gate called a buffer is manufactured to perform the same function as two inverters. Its symbol is simply a triangle, with no inverting "bubble" on the output terminal:

Figure 29. "Buffer" gate.

The internal schematic diagram for a typical open-collector buffer is not much different from that of a simple inverter: only one more common-emitter transistor stage is added to re-invert the output signal.

Figure 30. Buffer circuit with open collector output (A).

Let’s analyze this circuit for two conditions: an input logic level of "1" and an input logic level of "0." First, a "high" (1) input:

Figure 31. Buffer circuit with open collector output (B).

As before with the inverter circuit, the "high" input causes no conduction through the left steering diode of Q1 (emitter-to-base PN junction). All of R1's current goes through the base of transistor Q2, saturating it:

Figure 32. Buffer circuit with open collector output (C).

Having Q2 saturated causes Q3 to be saturated as well, resulting in very little voltage dropped between the base and emitter of the final output transistor Q4. Thus, Q4 will be in cutoff mode, conducting no current. The output terminal will be floating (neither connected to ground nor Vcc), and this will be equivalent to a "high" state on the input of the next TTL gate that this one feeds in to. Thus, a "high" input gives a "high" output.

With a "low" input signal (input terminal grounded), the analysis looks something like this:

Figure 33. Buffer circuit with open collector output (D).

All of R1's current is now diverted through the input switch, thus eliminating base current through Q2. This forces transistor Q2 into cutoff so that no base current goes through Q3 either. With Q3 cutoff as well, Q4 is will be saturated by the current through resistor R4, thus connecting the output terminal to ground, making it a "low" logic level. Thus, a "low" input gives a "low" output.

The schematic diagram for a buffer circuit with totem pole output transistors is a bit more complex, but the basic principles, and certainly the truth table, are the same as for the open-collector circuit:

Figure 34. Buffer circuit with totem pole output.

  • Two inverter, or NOT, gates connected in "series" so as to invert, then re-invert, a binary bit perform the function of a buffer. Buffer gates merely serve the purpose of signal amplification: taking a "weak" signal source that isn’t capable of sourcing or sinking much current, and boosting the current capacity of the signal so as to be able to drive a load.

  • Buffer circuits are symbolized by a triangle symbol with no inverter "bubble."

  • Buffers, like inverters, may be made in open-collector output or totem pole output forms.

4. Multiple-Input Gates

Inverters and buffers exhaust the possibilities for single-input gate circuits. What more can be done with a single logic signal but to buffer it or invert it? To explore more logic gate possibilities, we must add more input terminals to the circuit(s).

Adding more input terminals to a logic gate increases the number of input state possibilities. With a single-input gate such as the inverter or buffer, there can only be two possible input states: either the input is "high" (1) or it is "low" (0). As was mentioned previously in this chapter, a two input gate has four possibilities (00, 01, 10, and 11). A three-input gate has eight possibilities (000, 001, 010, 011, 100, 101, 110, and 111) for input states. The number of possible input states is equal to two to the power of the number of inputs:

Figure 35. The number of possible input states.

This increase in the number of possible input states obviously allows for more complex gate behavior. Now, instead of merely inverting or amplifying (buffering) a single "high" or "low" logic level, the output of the gate will be determined by whatever combination of 1’s and 0’s is present at the input terminals.

Since so many combinations are possible with just a few input terminals, there are many different types of multiple-input gates, unlike single-input gates which can only be inverters or buffers. Each basic gate type will be presented in this section, showing its standard symbol, truth table, and practical operation. The actual TTL circuitry of these different gates will be explored in subsequent sections.

4.1. The AND Gate

One of the easiest multiple-input gates to understand is the AND gate, so-called because the output of this gate will be "high" (1) if and only if all inputs (first input and the second input and . . .) are "high" (1). If any input(s) are "low" (0), the output is guaranteed to be in a "low" state as well.

Figure 36. Two-input and three-input AND gates.

In case you might have been wondering, AND gates are made with more than three inputs, but this is less common than the simple two-input variety.

A two-input AND gate’s truth table looks like this:

Figure 37. Two-input AND gate.

What this truth table means in practical terms is shown in the following sequence of illustrations, with the 2-input AND gate subjected to all possibilities of input logic levels. An LED (Light-Emitting Diode) provides visual indication of the output logic level:

Figure 38. Two-input AND gate LED output (A).
Figure 39. Two-input AND gate LED output (B).
Figure 40. Two-input AND gate LED output (C).
Figure 41. Two-input AND gate LED output (D).

It is only with all inputs raised to "high" logic levels that the AND gate’s output goes "high," thus energizing the LED for only one out of the four input combination states.

4.2. The NAND Gate

A variation on the idea of the AND gate is called the NAND gate. The word "NAND" is a verbal contraction of the words NOT and AND. Essentially, a NAND gate behaves the same as an AND gate with a NOT (inverter) gate connected to the output terminal. To symbolize this output signal inversion, the NAND gate symbol has a bubble on the output line. The truth table for a NAND gate is as one might expect, exactly opposite as that of an AND gate:

Figure 42. Two-input NAND.

As with AND gates, NAND gates are made with more than two inputs. In such cases, the same general principle applies: the output will be "low" (0) if and only if all inputs are "high" (1). If any input is "low" (0), the output will go "high" (1).

4.3. The OR Gate

Our next gate to investigate is the OR gate, so-called because the output of this gate will be "high" (1) if any of the inputs (first input or the second input or . . .) are "high" (1). The output of an OR gate goes "low" (0) if and only if all inputs are "low" (0).

Figure 43. Two-input and three-input OR gates.

A two-input OR gate’s truth table looks like this:

Figure 44. Two-input OR gate.

The following sequence of illustrations demonstrates the OR gate’s function, with the 2-inputs experiencing all possible logic levels. An LED (Light-Emitting Diode) provides visual indication of the gate’s output logic level:

Figure 45. Two-input OR gate LED output (A).
Figure 46. Two-input OR gate LED output (B).
Figure 47. Two-input OR gate LED output (C).
Figure 48. Two-input OR gate LED output (D).

A condition of any input being raised to a "high" logic level makes the OR gate’s output go "high," thus energizing the LED for three out of the four input combination states.

4.4. The NOR Gate

As you might have suspected, the NOR gate is an OR gate with its output inverted, just like a NAND gate is an AND gate with an inverted output.

Figure 49. Two-input NOR.

NOR gates, like all the other multiple-input gates seen thus far, can be manufactured with more than two inputs. Still, the same logical principle applies: the output goes "low" (0) if any of the inputs are made "high" (1). The output is "high" (1) only when all inputs are "low" (0).

4.5. The Negative-AND Gate

A Negative-AND gate functions the same as an AND gate with all its inputs inverted (connected through NOT gates). In keeping with standard gate symbol convention, these inverted inputs are signified by bubbles. Contrary to most peoples' first instinct, the logical behavior of a Negative-AND gate is not the same as a NAND gate. Its truth table, actually, is identical to a NOR gate:

Figure 50. Two-input negative-AND gate.

4.6. The Negative-OR Gate

Following the same pattern, a Negative-OR gate functions the same as an OR gate with all its inputs inverted. In keeping with standard gate symbol convention, these inverted inputs are signified by bubbles. The behavior and truth table of a Negative-OR gate is the same as for a NAND gate:

Figure 51. Two-input negative-OR gate.

4.7. The Exclusive-OR Gate

The last six gate types are all fairly direct variations on three basic functions: AND, OR, and NOT. The Exclusive-OR gate, however, is something quite different.

Exclusive-OR gates output a "high" (1) logic level if the inputs are at different logic levels, either 0 and 1 or 1 and 0. Conversely, they output a "low" (0) logic level if the inputs are at the same logic levels. The Exclusive-OR (sometimes called XOR) gate has both a symbol and a truth table pattern that is unique:

Figure 52. Exclusive-OR gate.

There are equivalent circuits for an Exclusive-OR gate made up of AND, OR, and NOT gates, just as there were for NAND, NOR, and the negative-input gates. A rather direct approach to simulating an Exclusive-OR gate is to start with a regular OR gate, then add additional gates to inhibit the output from going "high" (1) when both inputs are "high" (1):

Figure 53. Exclusive-OR gate equivalent circuit (A).

In this circuit, the final AND gate acts as a buffer for the output of the OR gate whenever the NAND gate’s output is high, which it is for the first three input state combinations (00, 01, and 10). However, when both inputs are "high" (1), the NAND gate outputs a "low" (0) logic level, which forces the final AND gate to produce a "low" (0) output.

Another equivalent circuit for the Exclusive-OR gate uses a strategy of two AND gates with inverters, set up to generate "high" (1) outputs for input conditions 01 and 10. A final OR gate then allows either of the AND gates' "high" outputs to create a final "high" output:

Figure 54. Exclusive-OR gate equivalent circuit (B).

Exclusive-OR gates are very useful for circuits where two or more binary numbers are to be compared bit-for-bit, and also for error detection (parity check) and code conversion (binary to Grey and vice versa).

4.8. The Exclusive-NOR Gate

Finally, our last gate for analysis is the Exclusive-NOR gate, otherwise known as the XNOR gate. It is equivalent to an Exclusive-OR gate with an inverted output. The truth table for this gate is exactly opposite as for the Exclusive-OR gate:

Figure 55. Exclusive-NOR gate.

As indicated by the truth table, the purpose of an Exclusive-NOR gate is to output a "high" (1) logic level whenever both inputs are at the same logic levels (either 00 or 11).


  • Rule for an AND gate: output is "high" only if first input and second input are both "high."

  • Rule for an OR gate: output is "high" if input A or input B are "high."

  • Rule for a NAND gate: output is not "high" if both the first input and the second input are "high."

  • Rule for a NOR gate: output is not "high" if either the first input or the second input are "high."

  • A Negative-AND gate behaves like a NOR gate.

  • A Negative-OR gate behaves like a NAND gate.

  • Rule for an Exclusive-OR gate: output is "high" if the input logic levels are different.

  • Rule for an Exclusive-NOR gate: output is "high" if the input logic levels are the same.

5. TTL NAND and AND Gates

Suppose we altered our basic open-collector inverter circuit, adding a second input terminal just like the first:

Figure 56. Two-input inverter circuit (A).

This schematic illustrates a real circuit, but it isn’t called a "two-input inverter." Through analysis we will discover what this circuit’s logic function is and correspondingly what it should be designated as.

Just as in the case of the inverter and buffer, the "steering" diode cluster marked "Q1" is actually formed like a transistor, even though it isn’t used in any amplifying capacity. Unfortunately, a simple NPN transistor structure is inadequate to simulate the three PN junctions necessary in this diode network, so a different transistor (and symbol) is needed. This transistor has one collector, one base, and two emitters, and in the circuit it looks like this:

Figure 57. Two-input inverter circuit (B).

In the single-input (inverter) circuit, grounding the input resulted in an output that assumed the "high" (1) state. In the case of the open-collector output configuration, this "high" state was simply "floating." Allowing the input to float (or be connected to Vcc) resulted in the output becoming grounded, which is the "low" or 0 state. Thus, a 1 in resulted in a 0 out, and vice versa.

Since this circuit bears so much resemblance to the simple inverter circuit, the only difference being a second input terminal connected in the same way to the base of transistor Q2, we can say that each of the inputs will have the same effect on the output. Namely, if either of the inputs are grounded, transistor Q2 will be forced into a condition of cutoff, thus turning Q3 off and floating the output (output goes "high"). The following series of illustrations shows this for three input states (00, 01, and 10):

Figure 58. Two-input inverter circuit (C).
Figure 59. Two-input inverter circuit (D).
Figure 60. Two-input inverter circuit (E).

In any case where there is a grounded ("low") input, the output is guaranteed to be floating ("high"). Conversely, the only time the output will ever go "low" is if transistor Q3 turns on, which means transistor Q2 must be turned on (saturated), which means neither input can be diverting R1 current away from the base of Q2. The only condition that will satisfy this requirement is when both inputs are "high" (1):

Figure 61. Two-input inverter circuit (F).

Collecting and tabulating these results into a truth table, we see that the pattern matches that of the NAND gate:

Figure 62. NAND gate.

In the earlier section on NAND gates, this type of gate was created by taking an AND gate and increasing its complexity by adding an inverter (NOT gate) to the output. However, when we examine this circuit, we see that the NAND function is actually the simplest, most natural mode of operation for this TTL design. To create an AND function using TTL circuitry, we need to increase the complexity of this circuit by adding an inverter stage to the output, just like we had to add an additional transistor stage to the TTL inverter circuit to turn it into a buffer:

Figure 63. AND gate circuit with open-collector output.

The truth table and equivalent gate circuit (an inverted-output NAND gate) are shown here:

Figure 64. AND gate.

Of course, both NAND and AND gate circuits may be designed with totem-pole output stages rather than open-collector. I am opting to show the open-collector versions for the sake of simplicity.


  • A TTL NAND gate can be made by taking a TTL inverter circuit and adding another input.

  • An AND gate may be created by adding an inverter stage to the output of the NAND gate circuit.

6. TTL NOR and OR Gates

Let’s examine the following TTL circuit and analyze its operation:

Figure 65. NOR gate circuit (A).

Transistors Q1 and Q2 are both arranged in the same manner that we’ve seen for transistor Q1 in all the other TTL circuits. Rather than functioning as amplifiers, Q1 and Q2 are both being used as two-diode "steering" networks. We may replace Q1 and Q2 with diode sets to help illustrate:

Figure 66. NOR gate circuit (B).

If input A is left floating (or connected to Vcc), current will go through the base of transistor Q3, saturating it. If input A is grounded, that current is diverted away from Q3's base through the left steering diode of "Q1," thus forcing Q3 into cutoff. The same can be said for input B and transistor Q4: the logic level of input B determines Q4's conduction: either saturated or cutoff.

Notice how transistors Q3 and Q4 are paralleled at their collector and emitter terminals. In essence, these two transistors are acting as paralleled switches, allowing current through resistors R3 and R4 according to the logic levels of inputs A and B. If any input is at a "high" (1) level, then at least one of the two transistors (Q3 and/or Q4) will be saturated, allowing current through resistors R3 and R4, and turning on the final output transistor Q5 for a "low" (0) logic level output. The only way the output of this circuit can ever assume a "high" (1) state is if both Q3 and Q4 are cutoff, which means both inputs would have to be grounded, or "low" (0).

This circuit’s truth table, then, is equivalent to that of the NOR gate:

Figure 67. NOR gate.

In order to turn this NOR gate circuit into an OR gate, we would have to invert the output logic level with another transistor stage, just like we did with the NAND-to-AND gate example:

Figure 68. OR gate circuit.

The truth table and equivalent gate circuit (an inverted-output NOR gate) are shown here:

Figure 69. OR gate.

Of course, totem-pole output stages are also possible in both NOR and OR TTL logic circuits.


  • An OR gate may be created by adding an inverter stage to the output of the NOR gate circuit.

7. CMOS Gate Circuitry

Up until this point, our analysis of transistor logic circuits has been limited to the TTL design paradigm, whereby bipolar transistors are used, and the general strategy of floating inputs being equivalent to "high" (connected to Vcc) inputs — and correspondingly, the allowance of "open-collector" output stages — is maintained. This, however, is not the only way we can build logic gates.

Field-effect transistors, particularly the insulated-gate variety, may be used in the design of gate circuits. Being voltage-controlled rather than current-controlled devices, IGFETs tend to allow very simple circuit designs. Take for instance, the following inverter circuit built using P- and N-channel IGFETs:

Figure 70. Inverter using IGFETs.

Notice the "Vdd" label on the positive power supply terminal. This label follows the same convention as "Vcc" in TTL circuits: it stands for the constant voltage applied to the drain of a field effect transistor, in reference to ground.

Let’s connect this gate circuit to a power source and input switch, and examine its operation. Please note that these IGFET transistors are E-type (Enhancement-mode), and so are normally-off devices. It takes an applied voltage between gate and drain (actually, between gate and substrate) of the correct polarity to bias them on.

Figure 71. The FET gate circuit with power and a switch (A).

The upper transistor is a P-channel IGFET. When the channel (substrate) is made more positive than the gate (gate negative in reference to the substrate), the channel is enhanced and current is allowed between source and drain. So, in the above illustration, the top transistor is turned on.

The lower transistor, having zero voltage between gate and substrate (source), is in its normal mode: off. Thus, the action of these two transistors are such that the output terminal of the gate circuit has a solid connection to Vdd and a very high resistance connection to ground. This makes the output "high" (1) for the "low" (0) state of the input.

Next, we’ll move the input switch to its other position and see what happens:

Figure 72. The FET gate circuit with power and a switch (B).

Now the lower transistor (N-channel) is saturated because it has sufficient voltage of the correct polarity applied between gate and substrate (channel) to turn it on (positive on gate, negative on the channel). The upper transistor, having zero voltage applied between its gate and substrate, is in its normal mode: off. Thus, the output of this gate circuit is now "low" (0). Clearly, this circuit exhibits the behavior of an inverter, or NOT gate.

Using field-effect transistors instead of bipolar transistors has greatly simplified the design of the inverter gate. Note that the output of this gate never floats as is the case with the simplest TTL circuit: it has a natural "totem-pole" configuration, capable of both sourcing and sinking load current. Key to this gate circuit’s elegant design is the complementary use of both P- and N-channel IGFETs. Since IGFETs are more commonly known as MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistor), and this circuit uses both P- and N-channel transistors together, the general classification given to gate circuits like this one is CMOS: Complementary Metal Oxide Semiconductor.

CMOS circuits aren’t plagued by the inherent nonlinearities of the field-effect transistors, because as digital circuits their transistors always operate in either the saturated or cutoff modes and never in the active mode. Their inputs are, however, sensitive to high voltages generated by electrostatic (static electricity) sources, and may even be activated into "high" (1) or "low" (0) states by spurious voltage sources if left floating. For this reason, it is inadvisable to allow a CMOS logic gate input to float under any circumstances. Please note that this is very different from the behavior of a TTL gate where a floating input was safely interpreted as a "high" (1) logic level.

This may cause a problem if the input to a CMOS logic gate is driven by a single-throw switch, where one state has the input solidly connected to either Vdd or ground and the other state has the input floating (not connected to anything):

Figure 73. CMOS inputs float.

Also, this problem arises if a CMOS gate input is being driven by an open-collector TTL gate. Because such a TTL gate’s output floats when it goes "high" (1), the CMOS gate input will be left in an uncertain state:

Figure 74. Open-collector TTL output to CMOS input.

Fortunately, there is an easy solution to this dilemma, one that is used frequently in CMOS logic circuitry. Whenever a single-throw switch (or any other sort of gate output incapable of both sourcing and sinking current) is being used to drive a CMOS input, a resistor connected to either Vdd or ground may be used to provide a stable logic level for the state in which the driving device’s output is floating. This resistor’s value is not critical: 10 kΩ is usually sufficient. When used to provide a "high" (1) logic level in the event of a floating signal source, this resistor is known as a pullup resistor:

Figure 75. Pullup resistor on CMOS input.

When such a resistor is used to provide a "low" (0) logic level in the event of a floating signal source, it is known as a pulldown resistor. Again, the value for a pulldown resistor is not critical:

Figure 76. Pulldown resistor on CMOS input.

Because open-collector TTL outputs always sink, never source, current, pullup resistors are necessary when interfacing such an output to a CMOS gate input:

Figure 77. Open-collector TTL output with pullup resistor to CMOS input.

Although the CMOS gates used in the preceding examples were all inverters (single-input), the same principle of pullup and pulldown resistors applies to multiple-input CMOS gates. Of course, a separate pullup or pulldown resistor will be required for each gate input:

Figure 78. Pullup resistors for a 3-input CMOS AND gate.

This brings us to the next question: how do we design multiple-input CMOS gates such as AND, NAND, OR, and NOR? Not surprisingly, the answer(s) to this question reveal a simplicity of design much like that of the CMOS inverter over its TTL equivalent.

For example, here is the schematic diagram for a CMOS NAND gate:

Figure 79. CMOS NAND gate circuit.

Notice how transistors Q1 and Q3 resemble the series-connected complementary pair from the inverter circuit. Both are controlled by the same input signal (input A), the upper transistor turning off and the lower transistor turning on when the input is "high" (1), and vice versa. Notice also how transistors Q2 and Q4 are similarly controlled by the same input signal (input B), and how they will also exhibit the same on/off behavior for the same input logic levels. The upper transistors of both pairs (Q1 and Q2) have their source and drain terminals paralleled, while the lower transistors (Q3 and Q4) are series-connected. What this means is that the output will go "high" (1) if either top transistor saturates, and will go "low" (0) only if both lower transistors saturate. The following sequence of illustrations shows the behavior of this NAND gate for all four possibilities of input logic levels (00, 01, 10, and 11):

Figure 80. Two-input CMOS NAND gate and output (A).
Figure 81. Two-input CMOS NAND gate and output (B).
Figure 82. Two-input CMOS NAND gate and output /©.
Figure 83. Two-input CMOS NAND gate and output (D).

As with the TTL NAND gate, the CMOS NAND gate circuit may be used as the starting point for the creation of an AND gate. All that needs to be added is another stage of transistors to invert the output signal:

Figure 84. CMOS AND gate circuit.

A CMOS NOR gate circuit uses four MOSFETs just like the NAND gate, except that its transistors are differently arranged. Instead of two paralleled sourcing (upper) transistors connected to Vdd and two series-connected sinking (lower) transistors connected to ground, the NOR gate uses two series-connected sourcing transistors and two parallel-connected sinking transistors like this: